1. Field of the Invention
Generally, the present disclosure relates to integrated circuits, and, more particularly, to the manufacture of field effect transistors in complex circuits including memory areas, for instance, in the form of a cache memory of a CPU.
2. Description of the Related Art
Integrated circuits comprise a large number of circuit elements on a given chip area according to a specified circuit layout, wherein transistor elements represent one of the dominant semiconductor elements in the integrated circuits. Hence, the characteristics of the individual transistors significantly affect overall performance of the complete integrated circuit. Generally, a plurality of process technologies are currently practiced, wherein, for complex circuitry, such as microprocessors, storage chips, ASICs (application specific ICs) and the like, CMOS technology is currently one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using CMOS technology, millions of complementary transistors, i.e., N-channel transistors and P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A MOS transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, comprises so-called PN junctions that are formed by an interface of highly doped drain and source regions with an inversely or weakly doped channel region disposed between the drain region and the source region. The conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed above the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on the dopant concentration, the mobility of the majority charge carriers and, for a given extension of the channel region in the transistor width direction, on the distance between the source and drain regions, which is also referred to as channel length.
On the other hand, the drive current capability of MOS transistors also depends on the transistor width, i.e., the extension of the transistor in a direction perpendicular to the current flow direction, so that the gate length, and thus the channel length, in combination with the transistor width, are dominant geometric parameters, which substantially determine the overall transistor characteristics, in combination with “transistor internal” parameters, such as overall charge carrier mobility, threshold voltage, i.e., a voltage at which a conductive channel forms below the gate insulation layer upon applying a control signal to the gate electrode, and the like. On the basis of field effect transistors, such as N-channel transistors and P-channel transistors, more complex circuit components are designed, depending on the overall circuit layout. For instance, storage elements in the form of registers and static RAM (random access memory) cells, represent important components of complex logic circuitries. For example, during the operation of complex CPU cores, a large amount of data has to be temporarily stored and retrieved, wherein the operating speed and the capacity of the storage elements have a significant influence on the overall performance of the CPU. Depending on the memory hierarchy used in a complex integrated circuit, different types of memory elements are used. For instance, registers and static RAM cells are typically used in the CPU core due to their superior access time, while dynamic RAM elements are preferably used as working memory due to the increased bit density compared to registers or static RAM cells. Typically, a dynamic RAM cell comprises a storage capacitor and a single transistor, wherein, however, a complex memory management system is required to periodically refresh the charge stored in the storage capacitors, which may otherwise be lost due to unavoidable leakage currents. Although the bit density of dynamic RAM devices may be very high, charge has to be transferred from and to the storage capacitors in combination with periodic refresh pulses, thereby rendering these devices less efficient in terms of speed and power consumption compared to static RAM cells. Thus, static RAM cells may be advantageously used as high speed memory with moderately high power consumption, while, however, requiring a plurality of transistor elements so as to allow the reliable storage of an information bit.
Consequently, a further increase in bit density of static memory areas requires the employment of field effect transistors of reduced dimensions and appropriate transistor performance with respect to operation speed, drive current capability and the like. For this purpose, frequently, the densely packed memory areas of semiconductor devices are provided as a bulk configuration, i.e., the active regions of the transistor devices are vertically restricted by well regions instead of a buried insulating layer, as is the case in silicon-on-insulator (SOI) configurations, while the lateral delineation of the active regions is accomplished on the basis of trench isolations. Although, in principle, SOI transistors may provide advantages in performance with respect to operating speed due to a reduced junction capacitance, which may be appropriate for transistors in speed critical signal paths, the transistors in static memory areas may have to be operated on the basis of stable threshold voltage conditions, which may not be efficiently met on the basis of an SOI configuration, unless the overall transistor dimensions are appropriately increased to take into consideration any threshold variations as may be caused by the so-called floating body effect. Since “bulk” transistors may provide superior inherent threshold stability, while the switching speed may be less critical compared to speed critical signal paths in logic portions of complex semiconductor devices, an increased transistor density and thus bit density may be accomplished on the basis of the bulk configuration.
In addition to reduced transistor dimensions for obtaining a high bit density, the wiring network in these densely packed device regions also has to be appropriately adapted to the reduced dimensions. Typically, most of the electrical interconnections between the individual semiconductor elements, such as the transistor elements, are provided on the basis of a stack of metallization layers, thereby requiring a complex metallization system, which may finally be connected to the individual circuit elements by using a contact structure, which may be understood as an interface between the actual semiconductor elements, such as transistors, capacitors and the like, and the complex wiring system. A corresponding contact structure comprises a plurality of contact elements formed in an interlayer dielectric material, which encloses and passivates the semiconductor elements. These contact elements are formed of any appropriate conductive material, such as tungsten, aluminum and the like, possibly in combination with an appropriate barrier material, and connect to specific contact areas of the circuit elements, such as gate electrode structures, drain and source regions of the transistors and the like. Due to the reduced transistor dimensions, in particular in densely packed static memory areas, the contact elements are to be adapted in size and position to the configuration of the densely packed transistors, while at the same time a space-efficient interconnection of the individual circuit elements is to be achieved. For this purpose, some contact elements may be appropriately configured in order to “directly” connect different circuit elements without requiring an additional connection to one or more of the above-lying metallization layers.
With reference to FIGS. 1a-1d, a typical design of a static memory cell in advanced semiconductor devices and corresponding manufacturing techniques will be described in more detail, thereby illustrating specific problems associated with complex contact structures, which may finally lead to significant yield losses.
FIG. 1a schematically illustrates a circuit diagram of a static RAM cell 150, as may typically be used in modern integrated circuits. The memory cell 150 comprises a storage element 151 which may include two inversely coupled inverters 152A, 152B, each of which includes a complementary transistor pair formed by a P-channel transistor 100P and an N-channel transistor 100N. The transistors 100P may also be referred to as “pull up” transistors, while the transistors 100N may be referred to as “pull down” transistors. Furthermore, the memory cell 150 comprises pass transistors 100A, which may connect the memory cell 151 to a bit line, indicated as BL, and an inverse bit line, indicated as BL, respectively. Thus, the gate electrodes of the pass transistors 100A may be considered as a word line, which may thus be enabled in order to perform read and write operations on the memory cell 151. As is evident from FIG. 1a, in addition to the six transistors 100P, 100N, 100A, a plurality of interconnections between these transistor elements is also required in order to realize the circuit design as illustrated in FIG. 1a. 
FIG. 1b schematically illustrates a top view of an actual semiconductor device or a layout thereof in which the memory cell 150, i.e., the six transistors, and a portion of the associated electrical connections is implemented. As illustrated, a plurality of active regions 102A, 102B, 102C and 102D are laterally delineated by an isolation structure 103, which is typically provided in the form of a shallow trench isolation comprised of any appropriate insulating material, such as silicon dioxide and the like. On the other hand, the active regions 102A, 102B, 102C, 102D are to be understood as silicon-based semiconductor areas in which appropriate dopant profiles are formed to obtain PN junctions in accordance with the required transistor characteristics. For example, the active region 102A may accommodate one of the pass transistors 100A and one of the pull down transistors 100N, which both represent N-channel transistors. Similarly, the active region 102D may accommodate the other pass transistor 100A and the other pull down transistor 100N. On the other hand, the active regions 102B, 102C may represent active regions for the P-channel transistors 100P, wherein the transistor characteristics, such as the width of the active regions 102A, 102B, 102C, 102D, are appropriately selected in order to obtain the desired circuit behavior. That is, typically, the pull down transistors 100N are provided as transistors having an increased transistor width in order to provide an enhanced switching time and drive current capability, for instance compared to the pass transistors 100A. Furthermore, the pull up transistors 100P have a reduced drive current compared to the transistors 100N due to the fact that the transistors 100P represent P-channel transistors and the width of the active regions 102B, 102C is less compared to the active regions 102A, 102D. Moreover, gate electrode structures 110 are formed above the active regions 102A, 102B, 102C, 102D and partially above the isolation structure 103 in accordance with transistor requirements. In order to reduce the number of additional metal lines in a metallization system, a respective one of the pull down transistors 100N shares a gate electrode structure 110 with a corresponding pull up transistor 100P, thereby providing electrical connections as required by the circuit diagram of FIG. 1a. Furthermore, a plurality of contact elements 121A, 121B are provided in order to contact the transistors 100N, 100P, 100A, i.e., the active regions 102A, 102B, 102C, 102D and/or corresponding gate electrode structures 110. For instance, “regular” contact elements 121A are provided to connect to the active regions of the transistors, i.e., to drain and/or source regions of these transistors, while the contact elements 121B have a specific design so as to connect an active region of one of the pull up transistors 100P with the gate electrode structure 110 of the other pull up transistor 100P and the associated pull down transistor 100N. Consequently, the contact elements 121B may be formed above the isolation structure 103 and a corresponding active region which, however, may result in increased yield losses, in particular when sophisticated transistor architectures are considered, as will be described in more detail with reference to FIGS. 1c and 1d. 
FIG. 1c schematically illustrates a cross-sectional view along the line Ic of FIG. 1b. As illustrated, a semiconductor device 100 comprising the memory cell 150 (FIG. 1b) comprises a substrate 101, such as a silicon substrate, an upper portion of which may represent a crystalline silicon-based semiconductor material 102. The isolation structure 103 laterally delineates the active region 102C within the semiconductor material 102, while a vertical extension of the active region 102C is defined by a well dopant species, such as an N-type dopant species, as the pull up transistor 100P represents a P-channel transistor, as previously discussed. In the manufacturing stage shown, the transistor 100P comprises drain and source regions 104, i.e., strongly P-doped regions which form, with the remaining portion of the active region 102C, respective PN junctions. Furthermore, a channel region 107 is located between the drain and source regions 104. Furthermore, the gate electrode structure 110 is formed above the active region 102C, wherein a gate electrode material 111 is separated from the channel region 107 by a gate dielectric material 112. It should be appreciated that the gate electrode material 111 and the gate dielectric material 112 may be provided in the form of any desired material or material composition, depending on the overall device requirements. For example, the gate dielectric material 112 may comprise a high-k dielectric material, i.e., a dielectric material having a dielectric constant of approximately 10.0 and higher, and the gate electrode material 111 may comprise a metal-containing material. In other cases, the gate electrode structure 110 has a more conventional configuration, i.e., the gate dielectric material 112 may be comprised of silicon dioxide, silicon nitride and the like, in combination with a polysilicon material and the like. Furthermore, a spacer structure 113 is formed on sidewalls of the gate electrode material 111 and is comprised of any appropriate material, such as silicon nitride, possibly in combination with etch stop materials in the form of silicon dioxide and the like. Furthermore, in this manufacturing stage, metal silicide regions 106 may be formed, at least in the drain and source regions 104, in order to reduce the overall series resistance of the transistor 100P and to provide low contact resistivity for any contact elements to be formed in a later manufacturing stage. As illustrated, the metal silicide 106 may also be formed in the gate electrode structure 110. It should be appreciated that a gate electrode structure 110 is also formed above the isolation structure 103 (see FIG. 1b) which extends into the active regions 102B and 102A, as previously explained.
In some examples, the transistor 100P may be formed on the basis of critical dimensions of approximately 50 nm and less, i.e., a length of the gate electrode material 111 may be 50 nm and less, thereby providing a high packing density in the memory cell 150 (see FIG. 1b). Moreover, frequently, the overall transistor performance may be enhanced by inducing a certain type of strain component in the channel region 107, which may be efficiently accomplished in P-channel transistors by incorporating a silicon/germanium alloy 105 in the drain and source regions 104. That is, due to the lattice mismatch between a silicon/germanium lattice and a silicon lattice, the material 105 has a strained state, which in turn induces a compressive strain component in the channel region 107, thereby increasing the charge carrier mobility, which in turn directly translates into an increased drive current capability and a higher switching speed.
Furthermore, the gate electrode structures 110 are embedded in an interlayer dielectric material 120, which may comprise an etch stop layer 122, such as a silicon nitride material and the like, in combination with a silicon dioxide material 123 and the like. It should be appreciated that a portion of the interlayer dielectric material 120 may also be used as a strain-inducing source, for instance, by providing the layer 122 in the form of a highly stressed dielectric material.
The semiconductor device 100 may be formed on the basis of any appropriate manufacturing regime, which may include sophisticated lithography and etch techniques for forming an isolation trench, which may subsequently be filled with an insulating material, thereby obtaining the isolation structure 103. Thereafter, the basic dopant concentration for the active region 102C and for any other active regions may be defined by ion implantation in combination with appropriately formed implantation masks. Next, the gate electrode structures 110 are formed by advanced lithography and etch techniques, followed by an appropriate process sequence for incorporating the silicon/germanium alloy 105 on the basis of selective epitaxial growth techniques. Thereafter, the drain and source regions 104 are formed in combination with the sidewall spacer structure 113, followed by a silicidation sequence for forming the regions 106. Thereafter, the interlayer dielectric material 120 may be deposited on the basis of any appropriate deposition technique, wherein well-established processes may be applied in order to obtain the desired configuration, for instance with respect to internal stress levels of the dielectric materials in the layer 120.
It should be appreciated that, due to the overall reduced device dimensions and the complex manufacturing sequence, tightly set process tolerances may have to be met in order to obtain the required device characteristics. For example, the process sequence for incorporating the silicon/germanium alloy 105 into the P-channel transistor 100P may require additional processes, which may result in a significant difference in topography between the isolation structure 103 and the active region 102C. Also, the silicidation process may result in a certain degree of non-uniformities of the metal silicide regions 106, in particular when nickel silicide is to be formed, which is typically used in view of superior conductivity compared to other metal silicide materials. Consequently, the further processing, i.e., the formation of contact elements in the interlayer dielectric material 120 so as to connect to the drain and source regions 104 and to the gate electrode 110 formed above the isolation structure 103, may have to be performed under very sophisticated conditions. Under these circumstances, in particular at the interface 103S, which delineates the active region 102C with respect to a length direction L of the active region 102C, contact failures may occur with increased probability upon forming the contact element 121B (see FIG. 1b) connecting the active region 102C, i.e., one of the regions 104, with the gate electrode 110 formed above the isolation structure 103.
FIG. 1d schematically illustrates the semiconductor device 100 with an etch mask 125 formed above the interlayer dielectric material 120 in order to define the lateral size and position of contact openings 120A, 120B, which are formed on the basis of an etch process 126, which is performed on the basis of an appropriate plasma assisted etch chemistry so as to etch through the material 123 and using the material 122 as an etch stop layer. Thereafter, the etch chemistry is appropriately selected so as to etch through the material 122, while using the metal silicide regions 106 as an etch stop. Moreover, in the contact opening 120B, the isolation structure 103 may also be partially exposed to the etch ambient and may result in undue material removal, in particular at the interface 103S, depending on the previously created surface topography and device characteristics, for instance with respect to the metal silicide 106 and the like. Furthermore, the spacer structure 113 above the isolation structure 103 may be eroded in a more or less pronounced degree, thereby also contributing to a further exposure of the region 103, which may result in undue material consumption during the etch process 126. Consequently, an additional cavity 120C may be formed in the isolation structure 103 and/or at an etch area of the active region 102C, wherein a depth of the cavity 120C may strongly depend on the previously created device configuration. In many cases, the cavity 120C may extend beyond the drain or source region 104, which may finally result in the creation of an additional leakage path after filling the contact openings 120B, 120A with a conductive material. In some cases, a total failure of the transistor 100P may be observed due to the short circuit between the drain and source region 104 and the remaining N-doped well region 102C due to the cavity 120C filled with the contact material. Consequently, upon further increasing the overall device density in static memory cells, even further sophisticated conditions may be created during the complex contact etch step, thereby resulting in additional yield losses, thereby rendering the conventional process strategy less attractive for further device scaling.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.